A flash memory is a solid-state device, which is a nonvolatile and rewritable memory that functions like a combination of RAM (random access memory) and a hard disk drive, and retains its data without power. In a similar structure to EEPROMs, it has address lines, data lines and control lines and can employ a single transistor for each of its memory cells for storing a bit of information. Address lines are unidirectional to the memory as an input and define the location where data is stored. Data lines are bidirectional and are used for the input and output of data. Control lines are used to specify a command for reading, programming and erasing. Flash memory is a fast growing segment of the semiconductor industry and has many uses in digital cameras, cell phones, printers, PDAs and audio recorders and players for storing software and data.
Flash memory offers extremely fast access time, low power consumption and is relatively immune to shock and vibration. Maintaining data integrity in a flash memory is an important issue in today's commercial and consumer electronic devices that employ flash memory.
There are three operational functions for a flash memory. The first function is the program (write) function for storing information or data to the memory cells. The second function is the read function, where the data that is previously stored is read from the device for external processing. The data is retained in the device after the program or read function is complete. The third function is an erase function, where the data is deleted from the memory cells and the memory cells are prepared for receiving new data.
A typical flash memory cell is shown in FIG. 2 of U.S. Pat. No. 5,365,486 (Schreck). This flash memory cell is a modified NMOS (N-channel metal-oxide semiconductor) transistor with a floating gate. The floating gate carries no negative charges and thus the raw state of the flash memory cells are 1's.
There are many ways to program, read, verify and refresh the contents of a cell in a flash memory. For example, FIG. 3a of U.S. Pat. No. 5,365,486 (Schreck) shows two separate voltage levels for the control gate voltage that are used for comparing the cell. First, the cell is read and compared to an elevated control gate voltage (42). As a result of this read operation, it determines if the memory cell contains data (44). If the memory cell contains data, then the next memory cell is processed (46). If the initial test found the cell does not contain data (44), then it reads the memory cell at a lower control gate voltage (48). After this read operation, it determines whether this memory cell contains data (50). If the memory cell does not contain data, then the next memory cell is processed (46). If the memory cell contains data, then it refreshes the memory cell (52) and the next memory cell is processed (46).
As shown in FIG. 3a of U.S. Pat. No. 5,365,486 (Schreck) and FIG. 1 of U.S. Pat. No. 5,768,193 (Lee et al.), each uses two different WL voltage (control gate voltage) levels to determine whether the cells require refreshing. Since each WL voltage has a settling time, this influences the speed by increasing the time it takes to complete the operation. In addition, the use of two WL voltage levels increases disturbance issues at the gate that affects reliability and data retention.